Metal-oxide semiconductors (MOS) are used for transistor devices in all types of electronic circuits designed today. A complementary MOS circuit (CMOS) connects a p-channel and an n-channel MOS transistor in a manner in which the input signal to the circuit is complemented and thereby performs an inverter function. The gates of the transistors in a conventional CMOS circuit are both connected to the input signal to the circuit. The collector ("drain") of one of transistors is connected to the ("drain") of the other transistor. The emitter ("source") of the p-channel transistor is connected to a logic high voltage source and the source of the n-channel transistor is connected to ground. When the p-channel transistor is on, the n-channel transistor is off and vice-versa. The output of the circuit therefore complements the input signal. In general the two transistors can be replaced with networks of transistors to realize other logic operations. Such a circuit is called a CMOS gate (or "device") of which the inverter is a special case.
The CMOS gate design is advantageous because it has extremely low power consumption. The low power consumption is an important reason why CMOS circuits are popular in calculators, digital watches and satellites, among other devices. CMOS technology is also advantageous in driver circuits, buffers, adders, microprocessors, memories and application specific integrated circuits. It is desirable to increase the speed of CMOS technology in order to speed up the circuit operation with respect to both circuit and device design. One way in which early CMOS circuits have become faster is by reducing the size of the CMOS circuits on the fabricated chip and therefore reducing the time required for a signal to travel within the circuit. While the speed of CMOS circuits have increased with this technique, the scaling of the size of the CMOS technology has many undesirable effects such as carrier drift, velocity saturation, trapping of hot carriers in the gate oxide and source-drain punch-through that have the effect of prohibiting substantially shorter channel lengths. These effects create a practical limitation on the minimum size of the CMOS circuits. Therefore, it would be desirable to improve the speed of the CMOS technology through a new circuit design.
The currently available CMOS logic circuit designs have similar operation speeds and one CMOS circuit does not have a significant speed advantage over another. Conventional circuit designs include complementary static logic, pseudo-NMOS logic, CMOS dynamic logic, transmission gate logic and CVSL logic. All the above logic circuits have substantially the same delay propagation mechanism between circuit stages. A stage is a distinct circuit element used in the circuit, e.g., an inverter stage. For a conventional CMOS circuit, the inverter stage includes the p-channel and n-channel transistors and their connectors. The output of the logic stages for conventional circuits switches from either V.sub.ss (logic low) to V.sub.dd (logic high) or vice-versa in response to an input signal. Due to the output load capacitance of the stage, the circuit requires the entire rising time t.sub.r or the entire falling time t.sub.f to make the entire transition between the logic states. In other words, the delay is produced by the t.sub.r or t.sub.f which is the time needed for the stage output to switch from rail to rail. The majority of this switching time from extreme levels of voltage is not utilized in the circuit and simply slows the operation. For example, if the input to a static CMOS inverter switches from logic low V.sub.ss to logic high V.sub.dd, the inverter output does not begin its transition until the input reaches 75% of V.sub.dd. Therefore, approximately 75% of the rise time is not utilized in the circuit operation.
It would be advantageous to design a circuit which could reduce the unproductive propagation delay time in the CMOS logic circuits and therefore increase the speed and efficiency of the overall circuit.